Clyde R. Visser, P.E.
VHDL Design and Modeling Tutorial for both the beginner and experienced Programmer using a Xilinx FPGA Development Board
Teach yourself the analysis and synthesis of digital systems using VHDL to design and simulate FPGA and VLSI digital systems. Participants learn the fundamental concepts of VHDL and practical design techniques using a Xilinx FPGA Development Board and ModelSim simulation software for hands-on experience. The VHDL methodology and design flow for logic synthesis addresses design issues related to component modeling, data flow description in VHDL and behavioral description of hardware. An emphasis is placed on understanding the hardware description language, VHDL design techniques for logic synthesis, design criteria, and VHDL applications.
At the end of this course, participants will be able to accomplish the following:
Even if you're now already familiar with VHDL but you've:
then this course will definitely have something for you as well. You will learn finite state machine design, the two-process design methodology, test-bench design, combinatorial and sequential logic, and extensible synthesizable designs that are reusable.
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