4 hours



Any Level




Clyde R. Visser, P.E.

VHDL Design and Modeling Tutorial for both the beginner and experienced Programmer using a Xilinx FPGA Development Board

Expected learning & outcomes

  • Describe and explain VHDL syntax and semantics
  • Create synthesizable designs using VHDL
  • Use Xilinx FPGA development board for hand-on experience
  • Design simple and practical test benches in VHDL
  • Use the Xilinx Vivado toolset
  • Design and develop VHDL models
  • Use ModelSim simulation software

    Skills you will learn

    Analysis, Development, Electrical engineering, Experience Design, Hardware, Library, Modeling Data, Reporting

    About this course

    Teach yourself the analysis and synthesis of digital systems using VHDL to design and simulate FPGA and VLSI digital systems. Participants learn the fundamental concepts of VHDL and practical design techniques using a Xilinx FPGA Development Board and ModelSim simulation software for hands-on experience. The VHDL methodology and design flow for logic synthesis addresses design issues related to component modeling, data flow description in VHDL and behavioral description of hardware. An emphasis is placed on understanding the hardware description language, VHDL design techniques for logic synthesis, design criteria, and VHDL applications.

    At the end of this course, participants will be able to accomplish the following:

    • Describe and explain VHDL syntax and semantics
    • Create synthesizable designs using VHDL
    • Use Xilinx FPGA development board for hand-on experience
    • Use the Xilinx ISE toolset
    • Use ModelSim simulation software
    • Design simple and practical test-benches in VHDL
    • Design and develop VHDL models


    • Familiarity with digital logic design, electrical engineering, or equivalent experience.

    Even if you're now already familiar with VHDL but you've:

    • Never used an attribute other than ‘event?
    • Never used variables?
    • Always used a process where a single concurrent statement would have sufficed?
    • Never used assert or report statements except (maybe) in a test-bench?
    • Never used an unconstrained vector or array?
    • Never used a passive process inside of an entity?
    • Never used a real or the math_real library package in synthesizable code?
    • Always used a single process per signal assignment?

    then this course will definitely have something for you as well. You will learn finite state machine design, the two-process design methodology, test-bench design, combinatorial and sequential logic, and extensible synthesizable designs that are reusable.


    Lore delivers value at the intersection of learning, interests and skills.

    Learn from Domain Experts

    Access learning options recommended by industry experts, professionals and thought leaders.

    Search & Compare

    Quickly search, select and add learning options to your learning list.

    Personalize your feed

    Tell us more about yourself to access the latest learning options, curated just for you.